Non-volatile memory (NVM) cells generally comprise transistors with programmable threshold voltages. For example, a floating gate transistor or a split gate transistor has a threshold voltage (Vt) that is programmed or erased by charging or discharging a floating gate located between a control gate and a channel in the transistor. Data is written in such memory cells by charging or discharging the floating gates of the memory cells to achieve threshold voltages corresponding to the data.
The act of programming the cell involves charging the floating gate with electrons, which increases the threshold voltage Vt. The act of erasing the cell involves removing electrons from the floating gate, which decreases the threshold voltage Vt.
One type of non-volatile cell is a nitride, read only memory (NROM) cell. Unlike a floating gate cell, the NROM cell has two separated and separately chargeable areas. Each chargeable area may define one bit or more. The separately chargeable areas are found within a nitride layer formed in an oxide-nitride-oxide (ONO) stack underneath the gate. When programming a bit, channel hot electrons are injected into the nitride layer. This is generally accomplished by the application of a positive gate voltage and positive drain voltage, the magnitude and duration of which are determined by different factors related to the amount of programming required.
However, during device fabrication, unintentional tunneling currents may be induced, resulting with cells charging, higher Vt and larger Vt variations between cells across the wafer. Such conditions may adversely impact device production.
After a stacked gate is formed, additional processing steps are performed to finish fabrication. For example, additional masking and etching may be required to form additional semiconductor structures or to deposit metal or polysilicon interconnections on a semiconductor device. When a device is exposed to plasma processing, e.g., plasma etching, electrical charges may accumulate on the interconnections due to a phenomenon referred to as the “antenna effect”. The accumulated charge on the interconnections creates a voltage difference across the ONO layer of a NROM memory cell. A sufficiently large voltage difference may cause tunneling current to flow through the ONO layer introducing a programming effect and altering the threshold voltage of the memory cell.
Methods have been described in the prior art for protecting memory cells from charging induced during device fabrication by limiting the accumulation of charge on device interconnections during fabrication and by dissipating any accumulated charge in a safe manner. For example, U.S. Pat. No. 6,869,844 to Liu, et al., assigned to Advanced Micro Device, Inc., describes a protective semiconductor structure for limiting and dissipating accumulated charge from the conductive interconnections in an NROM memory array. Protective structures are connected to the device interconnections to provide a discharge path for the accumulated charge without adversely affecting the normal operation of the semiconductor device. The discharge path is provided by a thin insulating layer between a conductive interconnection and the device substrate. The thin insulating layer is formed over a p-well formed in an n-well in the semiconductor substrate. The interconnection to be protected is formed so that a portion of the interconnection overlies the thin insulating layer. The structure forms a capacitor and back-to-back diodes connected in series between the protected interconnection and the substrate, providing a discharge path for built up charge on the interconnection.
Another example is U.S. patent application Ser. No. 20040007730 to Chou et al., assigned to Macronix of Taiwan, which describes a protection device for protecting against plasma and other related charge damages. The protection device basically includes back-to-back diodes and protection circuitry per word line. The protection device may be understood by referring to FIGS. 1 and 2. (FIG. 1 corresponds to FIG. 5 of U.S. patent application Ser. No. 20040007730.)
Reference is first made to FIG. 1. The structure of the protection device includes a semiconductor substrate 20 (PW) having an intrinsic p-type doping. A first deep n-type well 21 (NWD) and a second deep n-type well 22 (NWD) are formed by diffusion of n-type dopants into the substrate 20. A PMOS transistor 12 has a p-type source 23 and a p-type drain 24 formed within the first deep n-type well 21. An. n-type contact 25 is formed on the surface of the first deep n-type well 21. The p-type contact region 26 is formed in the surface of the substrate 20 (PW), preferably adjacent to the first deep n-type well 21. A gate 27 is formed over an insulator (not shown) between the source 23 and the drain 24 over the channel region. The first deep n-type well 21 acts as the semiconductor bulk within which the channel region is formed. The gate 27 is coupled to the first deep n-type well 21 via the contact 25. The source 23 is coupled to the substrate 20 via the contact 26, and to a ground reference. The drain 24 is coupled via a conductive line to a node 30 to be protected in integrated circuitry on the device. The gate 27 is also coupled to a circuit on the device which supplies the highest voltage VPCP11 available during operation. The voltage on the gate 27 is at least as high as the highest operating voltage applied to the node 30 during operation, and is high enough to bias the PMOS transistor 12 in a normally off position during operation of the device. During manufacture, node 30 is left floating.
Within the second deep n-type well 22, a deep p-type well 31 (PAW) is formed. An NMOS transistor 14 (also seen in FIG. 1) has a source 32 and a drain 33 formed within the p-type well 31 (PWI). A p-type contact 34 is formed by diffusion in the surface of the p-type well 31. Also, a p-type contact 35 is formed in the surface of the substrate 20, preferably adjacent to the second deep n-type well 22. A gate 36 is formed over an insulator (not shown) over the channel region between the source 32 and a drain 33 of the NMOS transistor 14. The gate 36 is coupled to the contact 34, so that the gate of the NMOS transistor 14 is coupled to the semiconductor bulk in which the channel of the NMOS transistor 14 is formed. The source 32 of the NMOS transistor 14 is coupled to the terminal 35 and to a ground reference. The drain 33 of the NMOS transistor 14 is coupled to the node 30. A contact 37 is formed in the surface of the second deep n-type well 22. The contact 37 is coupled to the highest voltage VPCP11 generated on that chip during operation, or to another voltage level sufficient to maintain isolation of the p-type well 31. The gate 36 of the NMOS transistor 14 is coupled to a circuit which supplies the lowest voltage NVPP provided on the chip, at least as low as the lowest voltage applied at the node 30 during operation, or to a circuit which provides a voltage low enough to turn off the NMOS transistor 14 during operation of the circuitry. During manufacturing, the gate 36 is left floating.
The gate insulator between the gate and channel of the NMOS transistor 14 and of the PMOS transistor 12 should be strong enough to withstand the high or low voltages applied during operation of the device. For example, the gate insulator comprises a relatively thick oxide, compared to gate oxide thicknesses for logic transistors, in one embodiment of the device.
As mentioned before, the protection device of U.S. patent application Ser. No. 20040007730 provides protection per word line. During positive charging, the PMOS transistor 12 turns on and clamps the high voltage. During negative charging, the NMOS transistor 14 turns on and clamps the high voltage. During product operation, the bipolar transistors PMOS and NMOS transistors 12 and 14 are turned off, due to voltages applied to the terminals VPCP11 and NVPP. For correct operation as a fuse one needs short channel devices (high β of the bipolar transistors). Careful optimization should be done on the Ld parameter, to provide the best tradeoff between efficient clamping and leakage at the off state.
Reference is now made to FIG. 2. In order to implement the above prior art structure per word line, a dedicated connectivity for each word line to each dedicated transistor is required. The area penalty is substantial, and may range between 2-20%, pending on various factors, e.g., the physical sector size (number and length of word lines) and design rules.